Invited lecture: 3D integration the building blocks of upcoming technologies

You are cordially invited to a lecture by Dr. Fabrice Nemouchi from CEA-LETI on Friday, the 20th of September.  The title of the lecture is ' 3D integration the building blocks of upcoming technologies'.  The abstract of the lecture and the short CV of Dr. Nemouchi are provided below. 

Location: The seminar hall of the Solid-State Electronics division (house 2, floor 1)

Time: 9:00 (sharp), Friday, 20th of Septemebr

Host: Zhen Zhang

Abstract:

The microelectronics industry and CMOS devices development most particularly, encountered drastic challenges on the down scale route in order to fulfil the specific requests that lead to low voltage, low power consumption and/or high performance devices. Thus, continuous modifications of Front-end (FEOL) and Back-end of line (BEOL) have been implemented during the two past decades while the typical pitch size of the device dropped below 90 nm. Moreover, those evolutions offer new paradigms architecture based on the FinFet and FD-SOI CMOS. Since a decade, a strong interest was figure out for the use of the third dimension as enhancer of performance increasing the transistors density at a given node. Indeed, the so-called 3D monolithic architecture or CoolCubeTM, consists in stacking a second transistors level on top of previous FD-SOI MOS layer, benefits on substantial rise of device numbers by cm2. Furthermore, the reduction of interconnects length and associated parasitics granted by the CoolCubeTM technology enables slightly relaxing the transistor dimensions, which is a considerable asset when processing more exotic materials. However, such smart architecture comes across new challenges due to the thermal budget that first process steps of the top transistors inflict to bottom ones. Although the thermal processing of top transistors is currently restricted with the goal of limiting the bottom CMOS degradation, the source and drain contacts appear to be a weak point that required an accurate attention.

The different approaches have been studied and set up to establish the first 3D circuit with optimize performances on both CMOS tiers:

• Increase the stability of the bottom CMOS and especially focus on the effort salicide module, since it appears as the Achilles’ heel on the first Tiers. Large studies on silicidation process and material behaviors will be presented to stabilize the Si and SiGe metallization. 

• Decrease the thermal budget required of the upper CMOS transistors processes such as Gate oxide annealing, dopant activation, spacer deposition, Source and drain epitaxies…

The presentation will focus on the main studies that was realized on the Si/SiGe 3D monolithic architecture so far.

  In  a second part, alternative channels could also be considers due to theirs mains properties. Indded, high mobility channels for advanced CMOS nodes have sparked significant interest over the past decade, since a larger drive current compared to Si-channel devices at a fixed gate overdrive allows maintaining the performance power dissipation trade-off while increasing circuit density. Based on their bulk electron and hole mobility, III-V materials (eg InGaAs) and Ge channels are generally considered among the most serious contenders, respectively for nFETs and pFETs. A 3D sequential integration with separately optimized nFET and pFET stages essentially boils down to solving issues of thermal budget compatibility between stages.

In this part, we will review some of the thermal budget constraints related to forming junctions on InGaAs and Ge (doping, epitaxy, intermetallic compound formation), and evaluate the corresponding impact on either a Ge-p-MOS-1st or III-V-nMOS-1st integration schemes.